一、設(shè)置差分線的方法 方法一： 1、LogicTAssign Differenttial Pair 2、在彈出的對話框里選擇需要添加的差分對，點(diǎn)擊Add按鈕，即可添加 方法二： 1、 SetupTConstraintsTElectrical 2、選擇 Net,然后在 Objec tsTCrea teTDifferen tt ial Pair 3 田 □ Rol □ S € S a ■ Add to F2 Pin Pair. Filler... :Worksheet sele :FC_MkIH_l VTO-FCB166 Filte「匚 re-apply J班 Edit IQbjecisI Column Vi ew Ana lyze Audit Tools Window Help Spacing 匚Set... 日 G Electri Referei Electrics 1…S 自“ ■ All Deselect p227-3PI IPC MAIN 1V0-PC B1 SDR (6J SD LVDS (15) DDR-A (24) DDn-K}(11J DI FF9O (2) DI FFPAIH5 DI FFPAI 麗 Net Class... C Ia5s--Clas5... Region... Region -Class... Regi on -Clas&-CI 自 s s, Net Group... Con str sint Set References... Change all design unit attributes Match Croup... Ratsnest Bundle. Differential Pair... Same Net Spacing CSet... Select Select and Show Element Objects Name Waive Restore DDR-D1 (11> DG*S1 N Group members... Rem oye Electrical CSet... Physical CSet... Expand Expand All Num 4- IMum - Rename. .Delete Create 白 0 Net Sig 白”■1® Tim i…s 由?蜃Rol 3、在彈出的對話框里選擇需要添加的差分對，點(diǎn)擊Create按鈕，即可添加 設(shè)置完差分線對后，需要設(shè)置其約束規(guī)則，方法如下： 1、初始默認(rèn)的有一個DEFAULT規(guī)則，右擊DEFAUIT，選擇CreateTPhysical CSet 2、彈出一下對話框，在Physical CSet欄寫上規(guī)則名稱，建議根據(jù)差分線的阻抗描寫，點(diǎn) 擊0K,這里已經(jīng)寫好，規(guī)則名稱為：DIFF100,就可以看到多了一行PCS Objects Type S Name 1! i Dsn 3 FC 2fiO7P AfiQ2M 1 VD PCS 田 DEFAULT PCS E DIFF1K 3、設(shè)立好規(guī)則后就可以在這項(xiàng)規(guī)則里設(shè)置線寬間距等參數(shù)了 4、在 Net 一欄看到有已經(jīng)設(shè)好的差分線，在 Referenced physical C Set 選項(xiàng)下選擇剛剛 設(shè)好的規(guī)則 DIFF100 n j Met [“■嗜 All I 町er5 3歸 Region All Layers Objects Refererwc-ed Physical CSel Line V Min Type S Name imm i ± Dsn 3 FC2M7P AR#23€ 1IW DEFAULT tt.soao DPr [J] LVD5CLK IDiFFIOT ? 9.1270 DPr |+| LVDSO DEFAULT 0.1270 DPr □ LVDS1 DIFFIM a. 1270 DPr F+l LVDS2 (Clear) 0.1270 DPr 田 LVD53 DIFFHH) &.1270 Net 1-JV3 DEFAULT 9.2000 Net i-5V DEFAULT G.20&0 Net ADC CH1 DEFAULT U.2CHM Net AGNO DEFAULT (J.2DUO *規(guī)則設(shè)置中各個項(xiàng)目的含義* Line Width （設(shè)置基本走線寬度） Min：最小線寬 Max:最大線寬，寫0相當(dāng)于無限大 Line Width Min IVlax mum mm 士 * 0.2000- DJKBM O.OOM 0,1270- O.WW Neck（neck 模式，一般在間距很小的時候用到） Min Width：最小線寬 Max Leng th：最大線長 FJeck Min \Ti-dth Max Lwngtli mim mim & 0.1270 0.000-0 <1.1575 O.IWWM} 012F0- o.ww Differential Pair （差分線設(shè)置，單端線可不寫） Min Line Spacing：差分對的最小線間距 Primary Gap：差分對理想線間距 Neck Gap :差分對最小允許線間距 （+）Tolerance :差分線允許的誤差+ （-）Tolerance :差分線允許的誤差- Differential Pair Min Line Spac Primary Gag N-eck Gap (+>r^lerariG§ (-^Tole 陽 nx miTil irnim mm mm irnim i. O.QQDd Q.OQO-Q O.DO-QO D.DQDO O.QDdQ 0.0000 0.0000 0.1524 fr.OTW O.WOT O.OTOT Vias （過孔選擇） BB Via St agger （設(shè)置埋/盲孔的過孔間距） Min：最小間距 Max：最大間距 BB Via ^ta-gger Min Max min mm ±. £ Q.1270 0.000-0 O.1270 0.<KWM> O.WW Allow Pad-Pad Connect： / Etch： / Ts： / Allow Pad-Pad Connect Et€ll Ts * ft ALL AL LOWED TRUE ANYWHERE ALL ALLO.? TRUE AHWVHEFtE ALL ALLO.? TRUE ANYWHEFtE 示意圖： PtiTTKllA'建 Lip Neck gap \eck Pi imary I ine width 二、設(shè)置等長 1、進(jìn)入規(guī)則設(shè)置頁面 Elec tricalTNe tTRo uti ngTRela tive Propaga tion Delay ■ e 1 - I - S - File Edit Objects Column View Analyze Audit Tools Window Help :s魚也■②瑪 _d偏2 “掩嫗金超嗚 :Worksheet selector Electrical 耳 j Net ■■■■S Rdative Propsgati□ n Delay □■■B Electrical Constraint Set Q signal Integrity H Timing 田?囉 Routing j ± B All Constraints S Signal Integrity 田?屢 Timing 白嚼 Routing s a s s s Wi-ing Vias Impedance Min/Max Propsgation Delays Total Etch Length Differencial Pair Objects Referenced Electrical C Set Type | s ? Name J Dsn 3 testzoi 70S Net VDDJVS Net VDD PLL 2W Net VDD IO 2V& Net VAA 2VB Net VAA PIX 2VB Net £PCLK LVD£P O Net SPCLK LVDS N O Net £ENSDR R£T Net SENSOR CLK Net SD LVDS P J Net SD LVDS P 2 Net SD LVDS P 1 Net SD LVDS P 0 Net SD LVDS N J Net SD LVDS N 2 Net SD LVDS N 1 Net SD LVDS N 0 PIR OUT 2、選中需要設(shè)置等長的網(wǎng)絡(luò)，右擊，選擇Crea teTMa tch Group Objects Referenced Electrical CSet Pin Pairs Pin Delay Pm 1 Pin 2 Type S Name mm mm A £ Dsn 3 test20170fl Net VDD 1Vfi Net VDD PLL 2VS Net VDD IO 2VS Net VAA 2VB Net VAA PIX 2VS SPCLK LVDS N 0 SENSOR RST SENSOR CLK Se ect and Show E ement Differential Pair... Electrical CSet... LVDS P LVDS LVDS P LVDS LVDS LVDS N LVDS LVDS P 3 OUT N1677S3271 N16BM797 N16S642OT N16552?014 N1684&B1I6 N16SO4^>61I N16B0-W9 N16&&3976 N16&03975 N167901S4 N167901S2 N167SM«3 N167W05 N1677S^&4 N16F7S41I2 N1677S265 N16773145 3、更改組名稱 Bookma『Ic … Expand Expand All Net Class... Add to... ? Remove R^n ame..? F2 Delete Create 直匚h Group... Net Group... 4、設(shè)置好后，會顯示MGrp，如下圖。這樣等長的線組就設(shè)好了，接下來是設(shè)置等長的約束 規(guī)則 Objects Referenced Electrical C Set Pin Pairs s Name A Dsn 3 te 81201703 MGrp 日 SENEOn LVDS (10) All Drivera?AII Reefe... N-et £P 匚 LK LV0S.P 0 All DrivarsyAII Reteivers N-et S.PC LK LVDS.N 0 All Drivers7AII Receivers N-et S.D LVDS P 3 All Drivers7AII Receivers N-et S.D LVD5 P 2 All Drivers7AII R&eeivers N-et S.D LVD5 PJ All Drivers7AII R&eeivers N-^t S-D LVDS P Q All Drivars/AII Receivers N-^t S-D LVDS N 3 All Drivars/AII Receivers N-et SD LVDS N 2 All Drivers/AII Rewivers N-et SD LVDS N 1 All Drivers/AII Rewivers Net SD LVD5 N 0 All Driwers/AII Receivers Net VDD 1Vfi N«t VDD PLL 2V8 N«t VDD_IO_2Va ^e-ltaiToler^riGe ns 5、在Delta:Tolerance〔 " I —欄設(shè)置好長度誤差范圍 ；ReTO陽ilCEHS ； :Elecirl&aJ cs$t Pin Pairs Pm Delay Scope Rtl£T|i, Pin it 1 Pin 2 DeltarT'oFrrjHice Type I S Marne mm 1 mm j,y x X X e ~[a Tj Dsin 3 t«st2ft17O9 ?ZIGrp 日 5EH5OR LVD5 |tD) All UrlversJAII Race... Global 0 na:B% Nei SPCLI£L訂理巴衛(wèi) AliDrr.era/AI Gbbal &ns:E% Net SPCLK LVD5 N 0 AllDrh'crs/AI Rccer^ra Qlc-iwl Cw:5 開 Nel: 5D LVDS P J AJ3 Drrs'era/AI Recar^ers G幅陽1 on^s%- Nel SD LUDS-P 2 AJIDrkers/AI Receivers Gbbal &ns:E% Net 50 lVDS P i AUDrrvcrs/AI Receriffira GlciMl TTmS%- Net SD.LVDS.P.fl AJ3 □rrs'era/AI Recar^ere GtDGl »n>a:5% Net SD LVDS N 3. AJIDrktrsXAl Receivers- Global 0RS：5% Nel 5O IVD5 N 2 AUDrr-tra/AI Receiver* GibtKil C- F5：5 % Net 5D LVD5 N 1 AJi Drri'era/AI Recar^ere Gt陽I N«t SD LUDS N O AJIDrktri/AI Receiv>=T& Gtbal QH£：5% Nel VDCL^ N«t V0D PLL 2V& MQW 越 越: 6、默認(rèn)的是以時間和百分比為單位，我們改成長度單位，如下圖 O 可 Eels ftefeTenced Electric^ CS-ec Pin Bai” Piil阿野 RmFHtfv Pml Pin 2 fclta：T(jh5r&ncc | Type S Nome mm jn. nd ns | j. ■ A X - a X X tan 3 iestMITOa MGrp 日 5EN£DR LVD5 (Ifl] All onv0(ra.°Air Rec«..? Global € FifH.H：0254 MM N$[ SPCLK LVD&P O Al DrfceffiJAIE HM令… Global fl MHHK254 UM Net SPCLK LyDS H D All Drivers All R已匚e... Global d MU^.254UM Ned! SD_LVDS_P_3 AH Driveins 'All^ Reac^.r Global 0 MM NE 50 LVD5 P 2 All Unvera Alf Rece..? Gtobal H MMA254 MM Nec SD LVDS PJ All DrEve<« All Rece Glotial d FJIMrfh.254 UM Nfft SCLLVDS_P_O Al Ifr-FwrsJAIIl RtWr.r Gbbal fl MMA.254MM Net SCLLVDS_N_3 All Dmers All^ Recc... Global Net SQ LVDS N 2 All Drivers Air R$ce. ih GtQhal U Mt/1：0.Z54 UM IMei SD LVDS N 1 AU Dr和即±311； Rece. .. Global 0 MUA.Z54 UM Nd SD_ILVDS_M_O AH Ekwicn 'Alli Recc^r Gk>t»l fl MM:0-.254MM Nel: VD©_1V.& Nec VDD PLL 2VB 7、然后設(shè)置一個網(wǎng)絡(luò)為目標(biāo)網(wǎng)絡(luò)，在網(wǎng)絡(luò)Delta:Tolerance欄處右鍵選擇Set as target. 如下圖 Rtijifrvi!： Dei， LVDG 匚述 LVDS. LVDS fteT-eranicecf Efeccrtcal 匚 Se：t Pi：r Pairs All Dri v9i'SfAf Ree&.ai All Dnv^rafAll Rece... All Drivers^AH Rece... Alli DnversfAU Rece... All Drivers^AII Rec&... All Dri v^isrAf All DnverafAll Rece... All Drivers^Ali Rece... AIL Dnversi'AU Rece... All Drivers^AII Rece... All DrtufirftrAl Reee... £D_LVD&_N_2 T侶 Ptnd | PmF mm. I th rn 5D_LVDS_P_11 SD_LVD5_P_fl- ?耳II」UIJ5；_M_：： VDD 1VB VOO_Pll_2V8 £D LW3 日 £ENSOft LVDS(10) SPCL&_LVD5_P_& 5PCLK_LVDS_O 化LUH P) GtobaF D MUlO.2B4 MU 甘 AA W3 VAA_PDt_ZVS SPCLKJLLfDS.P.fl 5iPC：LHJLVPHO SEHSOfMLK SD LVD& P 3 Gbobali GLOW Gbobat Gbot>aE GkMMl Gbabat Analyze Chsngei-- Formula... £ep«ndenciE5H. Ctd-hX Clrl+C Ctrl 理 InfcrmatiQn... Gtobaf GloEaT 5D_LV1?5_EJ MLLVIKJLI S l.i I ?“」：¥? F U 8、最后打開檢查模式，在Analyze菜單選擇Analysis Modes,彈出以下對話框，打開Relative propagation delay 三、過電阻等長設(shè)置 如下圖這種等長： 1、首先要創(chuàng)建電阻模型，點(diǎn)擊工具欄的Signal Model按鈕 2、找到電阻，點(diǎn)擊R0402_4_R0402_0 0,所有這種模型的電阻都高亮了 3、選中一個電阻，選擇 Create Model 4、進(jìn)入下一步，默認(rèn)，點(diǎn)擊 OK 兩T Create Device Model LJ evice FTopertl&s Ref Des R32 Device Tppe R0402_4_Ra402_0 CLASS DISCRETE VALUE 0 TERMI NAT0R_PACK FALSE Pin Count 2 C' Create IbisDevice model (* Create ESpiceDevice model UK. | Cancel I Help I 5、進(jìn)入下一步，默認(rèn)，點(diǎn)擊OK （注意：Value值不能為0） 6、依次把需要建立模型的電阻設(shè)好 7、這里可以看到我們剛剛設(shè)置好的XNet File Edit Objects Column View An.alyre Audit Tools Window Help 沖 0 B (5 ：電匚 :Worksheet selector 斗 * x 辱 ElectriuaJ || 巳“0 Electrical Constraint Set Ftl-C^ Signal [ntegrity 由?雇 Timing F+l -C^ R.o uting B-g! All Conslraints 自4陽 門“雇 Signal Integrity F+l-li^ Timing 白薩 Routing …“Q Wiring j…”§ Vias …“S Impedance […”S Nlin/Max Propagation Delay j…“S Total Etch Length 1…”3 Di-fferential Pair Relative- Pro-pagation Delay  3鵬2 3國|網(wǎng) test20LT08 Objects Type s Name Net IIR CTL Net IIR C1IT Net LECH Net LED- / XHet LVDSC B O XHet LVDSC P O XHet LVDS H O XHet LVDS H 1 XHet LVDS H 2 XHet LVDS H 3 XHet LVDS P O XHet LVDS P 1 XHet LVDS P 2 XHet LVDS_P_3 Net N16770-145 Net N1677&2fifi Net N1677&412 Net N1677&M4 8、選中網(wǎng)絡(luò)，右擊,Crea teTPin Pair,創(chuàng)建 Pin Pair 9、選擇兩個端點(diǎn)，點(diǎn)擊OK,這樣就添加好了。 I Create Pin Pairs of LVDSC_N_O First Pins: Second Pins: J15.9 ■ J15.9 | R3G.1 R3G.1 R36.2 U5.B4 Create on all valid worksheets Close I Help KNct 日 LVDSC H Q PPr IJ5.E4U15.9 10、依次創(chuàng)建其他XNet的Pin Pair JWet 日 LV&SC IJ O PPr U5.B4J15.9 XFJet 日 LV&SC P O PPr U5.A4;J15^ XN^t 日 LVDS B O PPr U5.aZJ15.15 XNet 曰 LV&5 B 1 PPr U5.a3:J15.12 XNet 曰 LV&S W 2 PPr U5.a5:J15.G XNet 曰 LV&5 N 3 PPr U5.B6J15Ji XFJet 曰 LV&5 P 0 PPr U5.A2:J1S,14 XFJet 日 LV&S P 1 PPr U5.A^:J15.11 畑t 日 LVD5 P 2 PPr U5.A5J15.& XNet 日 LV&5 P 3 PPr U5,A6;J15,2 11、選擇這些Pin Pair，右鍵創(chuàng)建Match Group met 田 LVDSC M met 田 LVD5C P met 田 LVDS N 0 met 田 LVDS N 1 met 田 LVDS N 2 met 田 LVDS N 3 met 田 LVDS P 0 met 田 LVDS P 1 met 田 LVDS P 2 met 田 LVDS_P_3 Net N1677S145 Net N1677S2&5 Net N16775412) Net N1677SM4 Net N16789705 Net N1678WG3 Net N16790132) Net N16790134) Net N16S03975 Net N16S03976 Net N16SM000 Net N16SM061 Net "1116345316) Net N16SS2014 Net N16S442M) Net N16S547&7 Net N16775327 Net PIH O1TT Net SEWSOR C Net sewsor r| Net VAA PIX： VAA 2V8 £e ect and Show E &ment Expand Expand All Ada to... Match Group... Net Group... Bookmark... Collap&e Rename... F2 Del ete Remove Constraint Set References... GigXplorer... Pin Pair... Differential P'air... Electrical CSet... 12 、最后，設(shè)置等長規(guī)則及目標(biāo)網(wǎng)絡(luò) 「「 □bjeccs Referenced] Ele&tricall C 曲 t Pin Delay RelaU1 Pin Pairs Piinl Pin ? Scope EtellaiTolcrflnw L Marne mm mm ng 1 * * R- * * * 日[est201T0a MGrp Id LVD5 (10| Al# EkirvcnsiAEI Ghbal 0 nsi5% LVDS P 3 AllOrwerBi'AI RBWhfgra Gbtal D ns:5 % XNct LUDS P 2 AJI Drr.'E-rXi'AI R-KEh Ers Ghbal Q ns:5 % XHet L 驅(qū) P 4 AllDrwerft'Ai RBceh'era Glob 刖 & ns:S % XNet LUD5 P 0 AJlDr^er&'AI FLecEhers Gbbal D ns:5 % Xliet WD5JL3 AH Orwcr^Al Rkcwcts EbbLl l> ns:S % XNet LVDS N 2 AJlDrr^er&i'AI Rece^ers Gbbai D ns:5 % XMrt IVDS H 1 AUDrwer^'AI Riscewens Ghb3l 0 ns:5 % XNet LVD&H 0 AllDrwtrBi'AI Rscehferg Glob-al D na:5 % XNet LUDSC_P_Q AJI DrrjerXi!AI Rmbers Ghbal D ns:5 % XH«t LUD£C_H_Q AllOrwer^AI RBcerw'eirs Glob-al & ns:5 %